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smcp0.2e fujitsu semiconductor data sheet 3stacked mcp (multi-chip packag e) flash & flash & fcram cmos 96m ( 16) page mode flash memory & 64m ( 16) flash memory & 64m ( 16) mobile fcram tm mb84vfaf5f5j1-70 features ? power supply voltage of 2.7 to 3.1v high performance 25 ns maximum page read access time, 65 ns maximum random a ccess time (flash_1) 70 ns maximum access time (flash_2) 65 ns maximum access time (fcram) operating temperature ?30 c to +85 c package 115-ball bga (continued) product lineup note:*1,all of v cc f_1, v cc f_2 and v cc r must be the same level when either part is being accessed. package flash_1 flash_2 fcram supply voltage (v) v cc f_1* = 3.0 v v cc f_2* = 3.0 v v cc r* = 3.0 v max. random address access time (ns) 65 70 65 max. page address access time (ns) 25 - - max. ce access time (ns) 65 70 65 max. oe access time (ns) 25 30 40 115-pin plastic fbga t.b.d. bga-115p-mxx +0.1v ?0.3 v +0.1v ?0.3 v +0.1v ?0.3 v
mb84vfaf5f5j1-70 2 (mb84vfaf5f5j1 smcp0.2e) (continued) ? flash memory two chip enable (ce0 f, ce1 f) ce0 f contorols 64mb. ce1 f controls 32mb region single 3.0 v read, program and erase minimized system level power requirements simultaneous read/write operations (dual bank) flexbank tm bank a: 12 mbit (ce0 f: 8 kb 8 and 64 kb 23) bank b: 36 mbit (ce0 f: 64 kb 72) bank c: 36 mbit (ce0 f: 64 kb 32, ce1: 64kb 40 ) bank d: 12 mbit (ce1 f 8 kb 8 and 64 kb 23) high performance page mode 25 ns maximum page access time (65 ns random access time) 8 words page minimum 100,000 program/erase cycles sector erase architecture eight 8 kbytes, a hundred eighty-four 64 kbytes, eight 8 kbytes sectors. any combination of sectors can be concurrent ly erased. also supports full chip erase dual boot block 16 to 8kbytes bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range hidden rom (hi-rom) region 256 byte of hi-rom, accessible throug h a new ?hi-rom enable? command sequence factory serialized and protected to provi de a secure electronic serial number (esn) wp /acc input pin at v il , allows protection of ?outermost? 2 16 k words on both ends of boot sectors, regardless of sector protection/unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance low v cc write inhibit 2.5 v embedded erase tm algorithms automatically preprograms and erases the chip or any sector embedded program tm algorithms automatically writes and verifies data at specified address data polling and toggle bit feature for detect ion of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion automatic sleep mode when addresses remain stable, the device auto matically switches itse lf to low power mode. program suspend/resume suspends the program operation to allow a read in another byte erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device hardware reset pin (reset ) hardware method to reset the device for reading array data new sector protection persistent sector protection password sector protection please refer to ?mbm29rm96df? datasheet in deteiled function
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 3 (continued) ? flash memory_2 simultaneous read / write operations ( dual bank ) flexbank tm bank a : 8 mbit (8 kb 8 and 64 kb 15) bank b : 24 mbit (64 kb 48) bank c : 24 mbit (64 kb 48) bank d : 8 mbit (8 kb 8 and 64 kb 15) two virtual banks are chosen from the combination of four physical banks. host system can program or erase in one bank, and t hen read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program minimum 100,000 program/erase cycles sector erase architecture sixteen 4 kword and one hundred twen ty-six 32 kword se ctors in word. any combination of sectors can be concurrently erased. it also supports full chip erase. hidden rom ( hi-rom ) region 256 byte of hi-rom, accessible throug h a new ?hi-rom enable? command sequence factory serialized and protected to provi de a secure electronic serial number (esn) wp / acc input pin at v il , allows protection of ?outermost? 2 8 kbytes on both ends of boot sectors, regardless of sector protection/ unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance embedded erase tm algorithms automatically preprograms and erases the chip or any sector embedded program tm algorithms automatically writes and verifies data at specified address data polling and toggle bit feature for detect ion of program or erase cycle completion ready / busy output (ry/by _1 or ry/by _2) hardware method for detection of program or erase cycle completion automatic sleep mode when addresses remain stable, the device auto matically switches itse lf to low power mode. low v cc f write inhibit 2.5 v program suspend / resume suspends the program operation to allow a read in another byte erase suspend / resume suspends the erase operation to allow a read data and/or program in another sector within the same device please refer to ?mbm29dl64df? datasheet in detailed function. (continued)
mb84vfaf5f5j1-70 4 (mb84vfaf5f5j1 smcp0.2e) (continued) ? fcram power dissipation operating : 25 ma max. standby : 200 a max. power down mode sleep : 10 a max. nap : 65 a max. 16m partial : 85 a max. power down control by ce2r byte write control: lb (dq 7 -dq 0 ), ub (dq 15 -dq 8 ) 8 words address access capability *: flexbank tm is a trademark of fujitsu limited, japan. *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. *: mobile fcram tm is a trademark of fujitsu limited, japan.
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 5 pin assignment (top view) marking side (bga-115p-mxx) d1 n.c. d8 a13 d7 a9 d6 a20 d5 ry/by_1 d4 a18 d3 a5 d2 d9 a21 f8 pe f7 dq6 f4 dq1 f3 vss f2 f9 a16 g8 dq15 g7 dq13 g6 dq4 g5 dq3 g4 dq9 g3 oe g2 g9 n.c. e8 a14 e7 a10 e4 a17 e3 a4 e2 e9 n.c. h8 dq7 h7 dq12 h6 vccr h5 vccf_1 h4 dq10 h3 dq0 h2 h9 vss j8 dq14 j7 dq5 j6 n.c. j5 dq11 j4 dq2 j3 dq8 c8 a12 c7 a19 c6 ce2r c5 reset_1 c4 ub c3 a6 a7 c2 c9 a15 a11 a8 we wp/acc lb f6 n.c. f5 n.c. e6 cef1_1 e5 n.c. n.c. n.c. n.c. n.c. b10 b9 a10 a9 n.c. n.c. n.c. n.c. cef_2 ry/by_2 j9 n.c. n.c. d10 n.c. f10 n.c. g10 n.c. e10 n.c. h10 n.c. c10 n.c. n.c. n.c. n.c. n.c. n.c. n.c. vccf_2 vss reset_2 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. j10 e1 f1 g1 h1 j1 j2 k10 k9 k8 l9 k1 n.c. n.c. b1 b2 a2 a1 n.c. l10 n.c. n.c. n.c. n10 n9 p9 n.c. p10 l1 k2 k3 k4 k5 k6 k7 n.c. n.c. n1 n2 l2 n.c. p1 p2 l3 l4 l5 l6 l7 l8 a2 a0 cef0_1 a1 ce1r a3 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. m1 m2 m3 m4 m5 m6 m7 m8 m9 m10
mb84vfaf5f5j1-70 6 (mb84vfaf5f5j1 smcp0.2e) pin description pin name input/ output description a 18 to a 0 i address inputs (common) a 21 to a 19 i address inputs (fcram & flash_1& flash_2 ) dq 15 to dq 0 i/o data inputs/outputs (common) ce f0_1 i chip enable (flash_1) ce f1_1 i chip enable (flash_1) ce f_2 i chip enable (flash_2) ce1 r i chip enable (fcram) ce2r i chip enable (fcram) oe i output enable (common) we i write enable (common) ry/by _1 o ready/busy output (fla sh_1) open drain output ry/by _2 o ready/busy output (fla sh_2) open drain output ub i upper byte control (fcram) lb i lower byte control (fcram) reset _1 i hardware reset pin/sector protection unlock (flash_1) reset _2 i hardware reset pin/sector protection unlock (flash_2) wp /acc i write protect / acceleration (flash_1& flash_2) pe i partial enable (fcram) n.c. ? no internal connection v ss power device ground (common) v cc f_1 power device power supply (flash_1) v cc f_2 power device power supply (flash_2) v cc r power device power supply (fcram)
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 7 block diagram v ss v cc r 64 m bit reset _2 flash memory_2 we 64 m bit fcram ce f_2 a 21 to a 0 oe ce1 r v ss v cc f_2 a 21 to a 0 dq 15 to dq 0 ry/by _2 lb ub wp /acc ce2r pe 96 m bit page mode v ss v cc f_1 a 21 to a 0 ce f1_1 reset _1 ry/by _1 ce f0_1 flash memory_1
mb84vfaf5f5j1-70 8 (mb84vfaf5f5j1 smcp0.2e) device bus operations (continued) operation (1), (2) ce f0_1 ce f1_1 ce f_2 ce1 r ce2r oe we lb ub pe a 21 to a 0 dq 7 to dq 0 dq 15 to dq 8 reset _1 reset _2 wp / acc(12) full standby h h h h h x x x x h x high-z high-z h h x output disable(3) hhh l hhhxx h x (10) high-z high-z h h x hhh h h hh x x x xxh h lhhh hh x x h l hh hhl h read from flash_1 (4) l h h h h l h x x h valid d out d out hhx h l h h h l h x x h valid d out d out hhx read from flash_2 (4) h h l h h l h x x h valid d out d out hhx write to flash _1 l h h h h h l x x h valid d in d in hhx h l h h h h l x x h valid d in d in hhx write to flash_2 h h l h h h l x x h valid d in d in hhx read from fcram(5) h h h l h l h l (9) l (9) h valid d out d out hhx write to fcram h h h l h h l ll h valid d in d in hhx h l high-z d in lh d in high-z
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 9 (continued) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except fo r indicated this column are inhibited. 2. do not apply for a following state two or more on the same time; 1) ce f0_1 = v il , 2) ce f1_1 = v il , 3)ce f_2 = v il , 4) ce 1r = v il and ce2r = v ih , 3. fcram output disable condition should not be kept longer than 1 s. 4. we can be v il if oe is v il , oe at v ih initiates the wr ite operations. 5. fcram lb , ub control at read operation is not supported. 6. it is also used for the ex tended sector group protections. 7. the fcram power down program can be performed one time after compliance of power-up timings and it should not be re-programmed after regular read or write. 8. fcram power down mode can be entered from standby state and all dq pins are in high-z state. i pd r current and data retention depends on the selection of power down program. 9. either or both lb and ub must be low for fcram read operation. 10. can be either v il or v ih but must be valid before read or write. 11. see ? fcram power do wn program key table ? in fcram part. 12. protect ? outer most ? 2x8k bytes ( 4 words ) on both ends of the boot block sectors. operation (1), (2) ce 0f_1 ce 1f_1 ce f_2 ce1 r ce2r oe we lb ub pe a 21 to a 0 dq 7 to dq 0 dq 15 to dq 8 reset _1 reset _2 wp / acc(12) flash_1 temporary sector group unprotection(6) x x x x x xxxxx x x x v id xx flash_ 2 temporary sector group unprotection(6) x x x x x xxxxx x x x x v id x flash_1 hardware reset x x x h h xxxxx x high- z high- z lxx flash_2 hardware reset x x x h h xxxxx x high- z high- z xlx flash_1 or 2 boot block sector write protection x x x x x xxxxx x x x x x l fcram power down program h h h h h xxxxl key (11) high- z high- z hhx fcram no read (7) h h h l h lhhhh valid high- z high- z hhx fcram power down (8) x x x x l xxxxx x x x x x x
mb84vfaf5f5j1-70 10 (mb84vfaf5f5j1 smcp0.2e) absolute maximum ratings *1 minimum dc voltage on input or i/o pins is ?0.3 v. duri ng voltage transitions, input or i/o pins may undershoot v ss to ?1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f_1 + 0.3 v or v cc f_2 + 0.3 v or v cc r + 0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f_1 + 2.0 v or v cc f_2 + 2.0 v or v cc r + 1.0 v for periods of up to 20 ns. *2: minimum dc input voltage on reset _1 or reset _2 pin is ?0.5 v. during voltage transitions reset _1 or reset _2 pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-v cc f_1 or v cc f_2) does not exceed +9.0 v. maximum dc input voltage on reset _1 or reset _2 pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is ?0.5 v. during voltage transitions, wp /acc pin may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f_1 or v cc f_2 is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operat ing conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warr anted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representa tives beforehand. note: operating ranges define those limits between which the functionality of the device is guaranteed. parameter symbol rating unit min. max. storage temperature tstg ?55 +125 c ambient temperature with power applied t a ?30 +85 c voltage with respect to ground all pins except reset _1 or reset _2,wp /acc * 1 v in , v out ?0.3 v cc f_1 +0.3 v v cc f_2 +0.3 v v cc r +0.3 v v cc f_1/v cc f_2/v cc r supply * 1 v cc f_1,v cc f_2, v cc r ?0.3 +3.3 v reset _1 or reset _2 * 2 v in ?0.5 + 13.0 v wp /acc * 3 v in ?0.5 +10.5 v parameter symbol value unit min. max. ambient temperature t a ?30 +85 c v cc f_1/v cc f_2/v cc r supply voltages v cc f_1,v cc f_2,v cc r+2.7 +3.1v
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 11 electrical characterist ics (dc characteristics) (continued) parameter sym- bol conditions value unit min. typ. max. input leakage current i li v in = v ss to v cc f_1,v cc r?1.0?+1.0 a output leakage current i lo v out = v ss to v cc f_1,v cc r?1.0?+1.0 a reset inputs leakage current (flash_1 & flash_2) i lit v cc f = v cc f max., reset = 12.5 v ??35a wp /acc acceleration program current (flash_1 & flash_2) i acc v cc f = v cc f max., wp /acc = v acc max. ??20ma flash_1 v cc active current (read) * 1 i cc1 f 1 ce (ce0 f or ce1 f) = v il , oe f= v ih f = 10 mhz ? ? 45 ma ce (ce0 f or ce1 f) = v il , oe f= v ih f = 5 mhz ? ? 20 ma flash_1 v cc active current * 2 i cc2 f 1 ce (ce0 f or ce1 f) = v il , oe f= v ih ??25ma v cc current (standby) i sb1 f 1 v cc f = v cc f max., ce0 f, ce1 f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v ?1 5a v cc current (standby,reset) i sb2 f 1 v cc f = v cc f max., reset = v ss 0.3 v, ?1 5a v cc current (automatic sleep mode)* 3 i sb3 f 1 v cc f = v cc f max., ce0 f, ce1 f= v ss 0.3 v, reset = v cc f 0.3 v, v in = v cc f 0.3 v or v ss f 0.3 v ?1 5a v cc active current (read-while-program)* 5 i cc3 f 1 ce (ce0 f or ce1 f) = v il , oe f= v ih ??45ma v cc active current (read-while-erase) i cc4 f 1 ce (ce0 f or ce1 f) = v il , oe f= v ih ??45ma v cc active current (erase-while-program)* 5 i cc5 f 1 ce (ce0 f or ce1 f) = v il , oe f= v ih ??25ma flash_2 v cc active current (read) * 1 i cc1 f 2 ce f = v il , oe = v ih t cycle =5 mhz ? ? 18 ma t cycle =1 mhz ? ? 4 ma flash_2 v cc active current (program/erase) * 2 i cc2 f 2 ce f = v il , oe = v ih ??35ma flash_2 v cc active current (read-while-program) * 5 i cc3 f 2 ce f = v il , oe = v ih ??53ma flash_2 v cc active current (read-while-erase) * 5 i cc4 f 2 ce f = v il , oe = v ih ??53ma flash_2 v cc active current (erase-suspend-program) i cc5 f 2 ce f = v il , oe = v ih ??40ma flash_2 v cc standby current i sb1 f v cc f = v cc f max., ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v ?1 * 7 5 * 7 a flash_2 v cc standby current (reset ) i sb2 f v cc f = v cc f max., reset = v ss 0.3 v, wp /acc = v cc f 0.3 v ?1 * 7 5 * 7 a flash_2 v cc current (automatic sleep mode) * 3 i sb3 f v cc f = v cc f max., ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v, v in = v cc f 0.3 v or v ss 0.3 v ?1 * 7 5 * 7 a fcram v cc active current i cc1 r v cc r = v cc r max., ce1 r = v il , ce2r = v ih, v in = v ih or v il , i out = 0ma t rc / t wc =min. ? ? 25 ma t rc / t wc =1 s ?? 3
mb84vfaf5f5j1-70 12 (mb84vfaf5f5j1 smcp0.2e) (continued) legend: flash means flash_1 or flash_2, v cc f means v cc f_1 or v cc f_2, v ss f means v ss f_1 or v ss f_2, ce f means ce f_1 or ce f _2, reset means reset _1 or reset _2 *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (pr ogram or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc f applying. *5: embedded alogorithm (program or erase) is in progress. (@5 mhz) *6: v cc indicates lower of v cc f_1 or v cc f_2 or v cc r. *7: actual standby current is twice of what is indicate d in the table, due to two flash memory chips embedment withn one device. parameter sym- bol conditions value unit min. typ. max. fcram v cc standby current i sb1 r v cc r = v cc r max.,ce1 r > v cc r ? 0.2v, ce2r > v cc r? 0.2v, v in < 0.2 v or v cc r ? 0.2 v ? ? 200 a fcram v cc power down current i pds r v cc r = v cc r max., ce1 r > v cc r ? 0.2v, ce2r < 0.2v, v in cycle time = t rc min. sleep ? ? 10 a i pdn rnap??65 a i pd8 r 16m partial ? ? 85 a input low level v il ? ?0.3 ? 0.5 v input high level v ih ?2.2? v cc + 0.3 * 6 v voltage for sector protection, and temporary sector unpro- tection (reset ) * 4 v id ? 11.5 12.0 12.5 v voltage for wp /acc sector pro- tection/unprotection and pro- gram acceleration * 4 v acc ?8.59.09.5v output low voltage level v ol f_1 v cc f = v cc f min., i ol =4.0 ma flash_1 ? ? 0.3 v v ol f_2 v cc f = v cc f min., i ol =4.0 ma flash_2 ? ? 0.45 v v ol rv cc r = v cc r min., i ol =1.0ma fcram ? ? 0.4 v output high voltage level v oh f_1 v cc f = v cc f min., i oh = ?2.0 ma flash_1 v cc f? 0.3 ??v v ol f_2 v cc f = v cc f min., i oh = ?2.0 ma flash_2 2.4 ? ? v v oh rv cc r = v cc r min., i oh =?0.5ma fcram 2.2 ? ? v flash low v cc f lock-out voltage v lko ?2.32.42.5v
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 13 electrical characterist ics (ac characteristics) ce timing timing diagram for alternating ram to flash_1 or flash_2 flash_1 characteristics please refer to ?96m page flash memory for mcp? part. in this part, flash means flash_1, v cc f means v cc f_1, v ss f means v ss f_1, ce f0 means ce f0_1, ce f0 means ce f1_1, reset means reset _1 flash_2 characteristics please refer to ?64m flash memory for mcp? part. in this part, flash means flash_2, v cc f means v cc f_2, v ss f means v ss f_2, ce f means ce f _2, reset means reset _2 fcram characteristics please refer to ?64m fcram for mcp? part. parameter symbol condition value unit jedec standard min. max. ce recover time ? t ccr ?0?ns ce hold time ? t chold ?3?ns ce1 r high to we invalid time for standby entry ?t chwx ?10?ns ce f0_1 or t ccr t ccr ce1 r ce2r t ccr t ccr we t chwx t chold ce f1_1 or ce f_2
96m page flash memory for mcp (96m flash for mcp) 1 smcp0.5e ? command definitions command sequence bus write cy- cles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h ra rd ? ? ? ? ? ? ? ? ? ? read/reset 3 555h aah 2aah 55h 555h f0h ra rd ? ? ? ? ? ? autoselect 3 555h aah 2aah 55h 555h 90h ? ? ? ? ? ? ? ? program 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? ? ? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h ? ? sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h ? ? program/erase suspend 1 bab0h???????????? program/erase resume 1 ba30h???????????? set to fast mode 3 555h aah 2aah 55h 555h 20h fast program 2 xxxh a0h pa pd reset from fast mode* 1 2 xxxh 90h xx 00h extended sector group protection* 2 4 xxxh 60h sga 60h sga 40h sga sd query 1 (ba) 55h 98h???????????? hi-rom entry 3 555h aah 2aah 55h 555h 88h ? ? ? ? ? ? ? ? hi-rom program* 3 4 555h aah 2aah 55h 555h a0h (hra) pa pd?????? hi-rom exit* 3 4 555h aah 2aah 55h 555h 90h xxxh 00h ? ? ? ? ? ? hi-rom protect* 3 6 555h aah 2aah 55h 555h 60h opbp 68h opbp 48h xxxh rd(0) ?? (continued)
96m page flash memory for mcp 2 (96m flash for mcp) smcp0.5e (continued) command definitions command sequence bus write cy- cles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data password program 4 555h aah 2aah 55h 555h 38h xx0hpd0?????? xx1hpd1?????? xx2hpd2?????? xx3hpd3?????? password unlock 7 555h aah 2aah 55h 555h 28h xx0h pd0 xx1h pd1 xx2h pd2 xx3h pd3 password verify 4 555h aah 2aah 55h 555h c8h pwa pwd ?????? password mode locking bit program 6 555h aah 2aah 55h 555h 60h pl 68h pl 48h xxh rd(0) ?? persistent protec- tion mode locking bit program 6 555h aah 2aah 55h 555h 60h spml 68h spml 48h xxh rd(0) ?? ppb program 6 555h aah 2aah 55h 555h 60h sa+wp 68h sa+wp 48h xxh rd(0) ?? ppb verify 4 555h aah 2aah 55h 555h 90h sa+x02 rd(0) ?????? all ppb erase 6 555h aah 2aah 55h 555h 60h wp 60h wp+sa 40h xxh rd(0) ?? ppb lock bit set 3 555h aah 2aah 55h 555h 78h ? ? ? ? ? ? ? ? ppb lock bit verify 4 555h aah 2aah 55h 555h 58h sa rd(1) ?????? dpb write 4 555h aah 2aah 55h 555h 48h sa x1h ? ? ? ? ? ? dpb erase 4 555h aah 2aah 55h 555h 48h sa x0h ? ? ? ? ? ? dpb verify 4 555h aah 2aah 55h 555h 58h sa rd(0) ??????
96m page flash memory for mcp (96m flash for mcp) 3 smcp0.5e legend: ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector . the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 will uniquely select any sector. ba = bank address. ad dress setted by a 21 , a 20 , a 19 , a 18 will select bank a, bank b, bank c and bank d. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. sga = sector group address to be protected. set sector group address and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0) sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hi-rom area 000000h to 00007fh hrba = bank address of the hi-rom area (a 21 = a 20 = a 19 = a 18 = v il ) rd (0) = read data bit. if programmed, dq 0 = 1, if erased, dq 0 = 0 rd (1) = read data bit. if programmed, dq 1 = 1, if erased, dq 1 = 0 opbp = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 1, 0, 1, 0) sla =address of the sector to be locked. set sector address (sa) and either a 6 = 1 for unlocked or a 6 = 0 for locked pwa/pwd = password ad dress/password data pl =(a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 0, 1, 0, 1, 0) spml = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 0, 0, 1, 0) wp =(a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 1, 1, 1, 0, 1, 0) *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: this command is valid during hi-rom mode. *4: the data ?00h? is also acceptable. notes : 1. address bits a 21 ="l", a 20 to a 11 = x = ?h? or ?l? for all address commands except for pa, sa, ba, sga, opbp, sla, pwa, pl, spml, wp. 2. bus operations are defined in table 2. 3. the system should generate the following address patterns: 555h or 2aah to addresses a 10 to a 0 4. both read/reset commands are functionally equivalent, resetting the device to the read mode. 5. a 21 must assert "l" to operate ce1 f region.
96m page flash memory for mcp 4 (96m flash for mcp) smcp0.5e sector group protection verify autoselect codes : *1 :sector group can be protected by "sector group protection", "extended sector group protection" and " new sector prot ection(ppb protection)". outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 :when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. cons equently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it becomes possible to activate simultaneous operation. *3 :a read cycle at address (ba) 01h outputs device code. when 227eh is outp ut, it indicates that two additional codes, called extended device codes, will be required. therefore the syst em may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh extenede auteselect code table type a 21 to a 12 a 6 a 5 a 4 a 3 a 2 a 1 a 0 code (hex) manufacture?s code ba *2 v il xx v il v il v il v il 04h device code ba *2 v il xx v il v il v il v ih 227eh extended device code *3 ba *2 v il xx v ih v ih v ih v ih 2217h ba *2 v il xx v ih v ih v ih v ih 2201h sector group protection *1 sector group addresses v il v ih v ih v ih v il v ih v il 01h *1 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer?s code 04h0000000000000100 device code 227eh0010001001111110 extended device code 2217h0010001000010111 2201h0010001000000001 ppb protection 01h 0000000000000001 ppb unprotection 00h 0000000000000000
96m page flash memory for mcp (96m flash for mcp) 5 smcp0.5e flexible sector-erase architecture sector address tables (bank a) bank sector chip enable sector address sector size (kwords) address range bank address ce0 ce1 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0 1 0 0 0 0 0 0 0 0 0 0 4 000000h to 000fffh sa1 0 1 0 0 0 0 0 0 0 0 0 1 4 001000h to 001fffh sa2 0 1 0 0 0 0 0 0 0 0 1 0 4 002000h to 002fffh sa3 0 1 0 0 0 0 0 0 0 0 1 1 4 003000h to 003fffh sa4 0 1 0 0 0 0 0 0 0 1 0 0 4 004000h to 004fffh sa5 0 1 0 0 0 0 0 0 0 1 0 1 4 005000h to 005fffh sa6 0 1 0 0 0 0 0 0 0 1 1 0 4 006000h to 006fffh sa7 0 1 0 0 0 0 0 0 0 1 1 1 4 007000h to 007fffh sa8 0 1 0 0 0 0 0 0 1 x x x 32 008000h to 00ffffh sa9 0 1 0 0 0 0 0 1 0 x x x 32 010000h to 017fffh sa10010000011xxx 32 018000h to 01ffffh sa11 0 1 0 0 0 0 1 0 0 x x x 32 020000h to 027fffh sa12010000101xxx 32 028000h to 02ffffh sa13 0 1 0 0 0 0 1 1 0 x x x 32 030000h to 037fffh sa14010000111xxx 32 038000h to 03ffffh sa15 0 1 0 0 0 1 0 0 0 x x x 32 040000h to 047fffh sa16010001001xxx 32 048000h to 04ffffh sa17 0 1 0 0 0 1 0 1 0 x x x 32 050000h to 057fffh sa18010001011xxx 32 058000h to 05ffffh sa19010001100xxx 32 060000h to 06ffffh sa20010001101xxx 32 068000h to 06ffffh sa21 0 1 0 0 0 1 1 1 0 x x x 32 070000h to 077fffh sa22010001111xxx 32 078000h to 07ffffh sa23 0 1 0 0 1 0 0 0 0 x x x 32 080000h to 087fffh sa24010010001xxx 32 088000h to 08ffffh sa25 0 1 0 0 1 0 0 1 0 x x x 32 090000h to 097fffh sa26 0 1 0 0 1 0 0 1 1 x x x 32 098000h to 09ffffh sa27010010100xxx 32 0a0000h to 0a7fffh sa28 0 1 0 0 1 0 1 0 1 x x x 32 0a8000h to 0affffh sa29010010110xxx 32 0b0000h to 0b7fffh sa30 0 1 0 0 1 0 1 1 1 x x x 32 0b8000h to 0bffffh
96m page flash memory for mcp 6 (96m flash for mcp) smcp0.5e (continued) sector address tables (bank b) bank sector chip enable sector address sector size (kwords) address range bank address ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa31 0 1 0011000xxx 32 0c0000h to 0c7 fffh sa32 0 1 0011001xxx 32 0c8000h to 0cffffh sa33 0 1 0011010xxx 32 0d0000h to 0d7 fffh sa34 0 1 0011011xxx 32 0d8000h to 0dffffh sa35 0 1 0011100xxx 32 0e0000h to 0e7fffh sa36 0 1 0011101xxx 32 0e8000h to 0effffh sa37 0 1 0011110xxx 32 0f0000h to 0f7fffh sa38 0 1 0011111xxx 32 0f8000h to 0ff fffh sa39 0 1 0100000xxx 32 100000h to 107fffh sa40 0 1 0100001xxx 32 108000h to 10 ffffh sa41 0 1 0100010xxx 32 110000h to 117fffh sa42 0 1 0100011xxx 32 118000h to 11 ffffh sa43 0 1 0100100xxx 32 120000h to 127fffh sa44 0 1 0100101xxx 32 128000h to 12 ffffh sa45 0 1 0100110xxx 32 130000h to 137fffh sa46 0 1 0100111xxx 32 138000h to 13 ffffh sa47 0 1 0101000xxx 32 140000h to 147fffh sa48 0 1 0101001xxx 32 148000h to 14 ffffh sa49 0 1 0101010xxx 32 150000h to 157fffh sa50 0 1 0101011xxx 32 158000h to 15 ffffh sa51 0 1 0101100xxx 32 160000h to 167fffh sa52 0 1 0101101xxx 32 168000h to 16 ffffh sa53 0 1 0101110xxx 32 170000h to 177fffh sa54 0 1 0101111xxx 32 178000h to 17 ffffh sa55 0 1 0110000xxx 32 180000h to 187fffh sa56 0 1 0110001xxx 32 188000h to 18 ffffh sa57 0 1 0110010xxx 32 190000h to 197fffh sa58 0 1 0110011xxx 32 198000h to 19 ffffh sa59 0 1 0110100xxx 32 1a0000h to 1a7fffh sa60 0 1 0110101xxx 32 1a8000h to 1affffh sa61 0 1 0110110xxx 32 1b0000h to 1b7fffh sa62 0 1 0110111xxx 32 1b8000h to 1bffffh sa63 0 1 0111000xxx 32 1c0000h to 1c7 fffh sa64 0 1 0111001xxx 32 1c8000h to 1cffffh sa65 0 1 0111010xxx 32 1d0000h to 1d7 fffh sa66 0 1 0111011xxx 32 1d8000h to 1dffffh sa67 0 1 0111100xxx 32 1e0000h to 1e7fffh sa68 0 1 0111101xxx 32 1e8000h to 1effffh sa69 0 1 0111110xxx 32 1f0000h to 1f7fffh sa70 0 1 0111111xxx 32 1f8000h to 1ff fffh sa71 0 1 1000000xxx 32 200000h to 207fffh
96m page flash memory for mcp (96m flash for mcp) 7 smcp0.5e (continued) bank sector chip enable sector address sector size (kwords) address range bank address ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa72 0 1 1000001xxx 32 208000h to 20 ffffh sa73 0 1 1000010xxx 32 210000h to 217 fffh sa74 0 1 1000011xxx 32 218000h to 21 ffffh sa75 0 1 1000100xxx 32 220000h to 227 fffh sa76 0 1 1000101xxx 32 228000h to 22 ffffh sa77 0 1 1000110xxx 32 230000h to 237 fffh sa78 0 1 1000111xxx 32 238000h to 23 ffffh sa79 0 1 1001000xxx 32 240000h to 247 fffh sa80 0 1 1001001xxx 32 248000h to 24 ffffh sa81 0 1 1001010xxx 32 250000h to 257 fffh sa82 0 1 1001011xxx 32 258000h to 25 ffffh sa83 0 1 1001100xxx 32 260000h to 267 fffh sa84 0 1 1001101xxx 32 268000h to 26 ffffh sa85 0 1 1001110xxx 32 270000h to 277 fffh sa86 0 1 1001111xxx 32 278000h to 27 ffffh sa87 0 1 1010000xxx 32 280000h to 287 fffh sa88 0 1 1010001xxx 32 288000h to 28 ffffh sa89 0 1 1010010xxx 32 290000h to 297 fffh sa90 0 1 1010011xxx 32 298000h to 29 ffffh sa91 0 1 1010100xxx 32 2a0000h to 2a7fffh sa92 0 1 1010101xxx 32 2a8000h to 2af fffh sa93 0 1 1010110xxx 32 2b0000h to 2b7fffh sa94 0 1 1010111xxx 32 2b8000h to 2bf fffh sa95 0 1 1011000xxx 32 2c0000h to 2c7fffh sa96 0 1 1011001xxx 32 2c8000h to 2cffffh sa97 0 1 1011010xxx 32 2d0000h to 2d7fffh sa98 0 1 1011011xxx 32 2d8000h to 2dffffh sa99 0 1 1011100xxx 32 2e0000h to 2e7fffh sa1000 1 1011101xxx 32 2e8000h to 2ef fffh sa1010 1 1011110xxx 32 2f0000h to 2f7fffh sa1020 1 1011111xxx 32 2f8000h to 2f ffffh
96m page flash memory for mcp 8 (96m flash for mcp) smcp0.5e (continued) sector address tables (bank c) bank sector chip enable sector address sector size (kwords) address range bank address ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa103 0 1 1 1 0 0 0 0 0 x x x 32 300000h to 307fffh sa1040 1 1100001xxx 32 308000h to 30ffffh sa105 0 1 1 1 0 0 0 1 0 x x x 32 310000h to 317fffh sa1060 1 1100011xxx 32 318000h to 31ffffh sa107 0 1 1 1 0 0 1 0 0 x x x 32 320000h to 327fffh sa1080 1 1100101xxx 32 328000h to 32ffffh sa109 0 1 1 1 0 0 1 1 0 x x x 32 330000h to 337fffh sa1100 1 1100111xxx 32 338000h to 33ffffh sa111 0 1 1 1 0 1 0 0 0 x x x 32 340000h to 347fffh sa1120 1 1101001xxx 32 348000h to 34ffffh sa113 0 1 1 1 0 1 0 1 0 x x x 32 350000h to 357fffh sa1140 1 1101011xxx 32 358000h to 35ffffh sa115 0 1 1 1 0 1 1 0 0 x x x 32 360000h to 367fffh sa1160 1 1101101xxx 32 368000h to 36ffffh sa117 0 1 1 1 0 1 1 1 0 x x x 32 370000h to 377fffh sa1180 1 1101111xxx 32 378000h to 37ffffh sa119 0 1 1 1 1 0 0 0 0 x x x 32 380000h to 387fffh sa1200 1 1110001xxx 32 388000h to 38ffffh sa121 0 1 1 1 1 0 0 1 0 x x x 32 390000h to 397fffh sa1220 1 1110011xxx 32 398000h to 39ffffh sa123 0 1 1 1 1 0 1 0 0 x x x 32 3a0000h to 3a7fffh sa124 0 1 1 1 1 0 1 0 1 x x x 32 3a8000h to 3affffh sa125 0 1 1 1 1 0 1 1 0 x x x 32 3b0000h to 3b7fffh sa126 0 1 1 1 1 0 1 1 1 x x x 32 3b8000h to 3bffffh sa127 0 1 1 1 1 1 0 0 0 x x x 32 3c0000h to 3c7fffh sa128 0 1 1 1 1 1 0 0 1 x x x 32 3c8000h to 3cffffh sa129 0 1 1 1 1 1 0 1 0 x x x 32 3d0000h to 3d7fffh sa130 0 1 1 1 1 1 0 1 1 x x x 32 3d8000h to 3dffffh sa131 0 1 1 1 1 1 1 0 0 x x x 32 3e0000h to 3e7fffh sa132 0 1 1 1 1 1 1 0 1 x x x 32 3e8000h to 3effffh sa133 0 1 1 1 1 1 1 1 0 x x x 32 3f0000h to 3f7fffh sa134 0 1 1 1 1 1 1 1 1 x x x 32 3f8000h to 3fffffh sa135 1 0 0 0 0 0 0 0 0 x x x 32 400000h to 407fffh sa1361 0 0000001xxx 32 408000h to 40ffffh sa137 1 0 0 0 0 0 0 1 0 x x x 32 410000h to 417fffh sa1381 0 0000011xxx 32 418000h to 41ffffh sa139 1 0 0 0 0 0 1 0 0 x x x 32 420000h to 427fffh sa1401 0 0000101xxx 32 428000h to 42ffffh sa141 1 0 0 0 0 0 1 1 0 x x x 32 430000h to 437fffh sa1421 0 0000111xxx 32 438000h to 43ffffh sa143 1 0 0 0 0 1 0 0 0 x x x 32 440000h to 447fffh
96m page flash memory for mcp (96m flash for mcp) 9 smcp0.5e (continued) bank sector chip enable sector address sector size (kwords) address range bank addres ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa1441 0 0001001xxx 32 448000h to 44ffffh sa1451 0 0001010xxx 32 450000h to 457fffh sa1461 0 0001011xxx 32 458000h to 45ffffh sa1471 0 0001100xxx 32 460000h to 467fffh sa1481 0 0001101xxx 32 468000h to 46ffffh sa1491 0 0001110xxx 32 470000h to 477fffh sa1501 0 0001111xxx 32 478000h to 47ffffh sa1511 0 0010000xxx 32 480000h to 487fffh sa1521 0 0010001xxx 32 488000h to 48ffffh sa1531 0 0010010xxx 32 490000h to 497fffh sa1541 0 0010011xxx 32 498000h to 49ffffh sa1551 0 0010100xxx 32 4a0000h to 4a7fffh sa1561 0 0010101xxx 32 4a8000h to 4a ffffh sa1571 0 0010110xxx 32 4b0000h to 4b7fffh sa1581 0 0010111xxx 32 4b8000h to 4b ffffh sa1591 0 0011000xxx 32 4c0000h to 4c7fffh sa1601 0 0011001xxx 32 4c8000h to 4c ffffh sa1611 0 0011010xxx 32 4d0000h to 4d7fffh sa1621 0 0011011xxx 32 4d8000h to 4d ffffh sa1631 0 0011100xxx 32 4e0000h to 4e7fffh sa1641 0 0011101xxx 32 4e8000h to 4e ffffh sa1651 0 0011110xxx 32 4f0000h to 4f7 fffh sa1661 0 0011111xxx 32 4f8000h to 4 fffffh sa1671 0 0100000xxx 32 500000h to 507fffh sa1681 0 0100001xxx 32 508000h to 50ffffh sa1691 0 0100010xxx 32 510000h to 517fffh sa1701 0 0100011xxx 32 518000h to 51ffffh sa1711 0 0100100xxx 32 520000h to 527fffh sa1721 0 0100101xxx 32 528000h to 52ffffh sa1731 0 0100110xxx 32 530000h to 537fffh sa1741 0 0100111xxx 32 538000h to 53ffffh
96m page flash memory for mcp 10 (96m flash for mcp) smcp0.5e sector address tables (bank d) bank sector chip enable sector address sector size (kwords) address range bank address ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1751 0 0101000xxx 32 540000h to 547fffh sa1761 0 0101001xxx 32 548000h to 54 ffffh sa1771 0 0101010xxx 32 550000h to 557fffh sa1781 0 0101011xxx 32 558000h to 55 ffffh sa1791 0 0101100xxx 32 560000h to 567fffh sa1801 0 0101101xxx 32 568000h to 56 ffffh sa1811 0 0101110xxx 32 570000h to 577fffh sa1821 0 0101111xxx 32 578000h to 57 ffffh sa1831 0 0110000xxx 32 580000h to 587fffh sa1841 0 0110001xxx 32 588000h to 58 ffffh sa1851 0 0110010xxx 32 590000h to 597fffh sa1861 0 0110011xxx 32 598000h to 59 ffffh sa1871 0 0110100xxx 32 5a0000h to 5a7 fffh sa1881 0 0110101xxx 32 5a8000h to 5affffh sa1891 0 0110110xxx 32 5b0000h to 5b7 fffh sa1901 0 0110111xxx 32 5b8000h to 5bffffh sa1911 0 0111000xxx 32 5c0000h to 5c7 fffh sa1921 0 0111001xxx 32 5c8000h to 5cffffh sa1931 0 0111010xxx 32 6d0000h to 5d7 fffh sa1941 0 0111011xxx 32 6d8000h to 5dffffh sa1951 0 0111100xxx 32 5e0000h to 5e7 fffh sa1961 0 0111101xxx 32 5e8000h to 5effffh sa1971 0 0111110xxx 32 5f0000h to 5f7fffh sa1981 0 0111111000 4 5f8000h to 5f8fffh sa1991 0 0111111001 4 5f9000h to 5f9fffh sa2001 0 0111111010 4 5fa000h to 5fa fffh sa2011 0 0111111011 4 5fb000h to 5fb fffh sa2021 0 0111111100 4 5fc000h to 5fcfffh sa2031 0 0111111101 4 5fd000h to 5fdfffh sa2041 0 0111111110 4 5fe000h to 5fe fffh sa2051 0 0111111111 4 5ff000h to 5 fffffh
96m page flash memory for mcp (96m flash for mcp) 11 smcp0.5e (continued) sector group address table sector group ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0010000000000 sa0 sga1010000000001 sa1 sga2010000000010 sa2 sga3010000000011 sa3 sga4010000000100 sa4 sga5010000000101 sa5 sga6010000000110 sa6 sga7010000000111 sa7 sga80100000 01 xxx sa8 to sa10 10 11 sga90100001x xxxxsa11 to sa14 sga100100010x xxxxsa15 to sa18 sga110100011x xxxxsa19 to sa22 sga120100100x xxxxsa23 to sa26 sga130100101x xxxxsa27 to sa30 sga140100110x xxxxsa31 to sa34 sga150100111x xxxxsa35 to sa38 sga160101000x xxxxsa39 to sa42 sga170101001x xxxxsa43 to sa46 sga180101010x xxxxsa47 to sa50 sga190101011x xxxxsa51 to sa54 sga200101100x xxxxsa55 to sa58 sga210101101x xxxxsa59 to sa62 sga220101110x xxxxsa63 to sa66 sga230101111x xxxxsa67 to sa70 sga240110000x xxxxsa71 to sa74 sga250110001x xxxxsa75 to sa78
96m page flash memory for mcp 12 (96m flash for mcp) smcp0.5e (continued) (continued) sector group ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga260110010x xxxxsa79 to sa82 sga270110011x xxxxsa83 to sa86 sga280110100x xxxxsa87 to sa90 sga290110101x xxxxsa91 to sa94 sga300110110x xxxxsa95 to sa98 sga310110111x xxxxsa99 to sa102 sga320111000x xxxxsa103 to sa106 sga330111001x xxxxsa107 to sa110 sga340111010x xxxxsa111 to sa114 sga350111011x xxxxsa115 to sa118 sga360111100x xxxxsa119 to sa122 sga370111101x xxxxsa123 to sa126 sga380111110x xxxxsa127 to sa130 sga390111111x xxxxsa131 to sa134 sga401000000x xxxxsa135 to sa138 sga411000001x xxxxsa139 to sa142 sga421000010x xxxxsa143 to sa146 sga431000011x xxxxsa147 to sa150 sga441000100x xxxxsa151 to sa154 sga451000101x xxxxsa155 to sa158 sga461000110x xxxxsa159 to sa162 sga471000111x xxxxsa163 to sa166 sga481001000x xxxxsa167 to sa170 sga491001001x xxxxsa171 to sa174
96m page flash memory for mcp (96m flash for mcp) 13 smcp0.5e (continued) sector group ce0 fce1 f a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga50 0 1 01010 xxxxxsa175 to sa178 sga51 0 1 01011 xxxxxsa179 to sa182 sga52 0 1 01100 xxxxxsa183 to sa186 sga53 0 1 01101 xxxxxsa187 to sa190 sga54 0 1 01110 xxxxxsa191 to sa194 sga55 01 01111 00 x x x sa195 to sa197 01 01 01 10 sga56 0 1 0111111000 sa198 sga57 0 1 0111111001 sa199 sga58 0 1 0111111010 sa200 sga59 0 1 0111111011 sa201 sga60 0 1 0111111100 sa202 sga61 0 1 0111111101 sa203 sga62 1 0 0111111110 sa204 sga63 1 0 0111111111 sa205
96m page flash memory for mcp 14 (96m flash for mcp) smcp0.5e ac characteristics read only operations characteristics parameter symbol conditions value(note) unit jedec standard min. max. read cycle time t avav t rc ?65?ns address to output delay t avqv t acc ce0 f or ce1 f = v il oe = v il ?65ns page read cycle time ? t prc ?25?ns page address to output delay ? t pacc ce0 f or ce1 f= v il oe = v il ?25ns chip enable to output delay t elqv t ce oe = v il ?65ns output enable to output delay t glqv t oe ??25ns chip enable to output high-z t ehqz t df ??25ns output enable to output high-z t ghqz t df ??25ns output hold time from address, ce (ce0 f or ce1 f) or oe , whichever occurs first t axqx t oh ?0?ns reset pin low to read mode ? t ready ??20s note: test conditions: output load: v cc f =2.7 v to 3.1 v :1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc f timing measurement reference level input: 0.5 v cc f output: 0.5 v cc f
96m page flash memory for mcp (96m flash for mcp) 15 smcp0.5e write (erase/program) operations (continued) parameter symbols value unit jedec standard min. typ. max. write cycle time t avav t wc 65 ? ? ns address setup time t avwl t as 0??ns address setup time to oe low during toggle bit polling ?t aso 12 ? ? ns address hold time t wlax t ah 45 ? ? ns address hold time from ce or oe high during toggle bit polling ?t aht 0??ns data setup time t dvwh t ds 35 ? ? ns data hold time t whdx t dh 0??ns output enable hold time read ?t oeh 0??ns toggle and data polling 10 ? ? ns ce high during toggle bit polling ? t ceph 20 ? ? ns oe high during toggle bit polling ? t oeph 20 ? ? ns read recover time before write t ghwl t ghwl 0??ns read recover time before write t ghel t ghel 0??ns ce setup time t elwl t cs 0??ns we setup time t wlel t ws 0??ns ce hold time t wheh t ch 0??ns we hold time t ehwh t wh 0??ns write pulse width t wlwh t wp 35 ? ? ns ce pulse width t eleh t cp 35 ? ? ns write pulse width high t whwl t wph 30 ? ? ns ce pulse width high t ehel t cph 30 ? ? ns word programming operation t whwh1 t whwh1 ?6?s sector erase operation* 1 t whwh2 t whwh2 ?0.5? s v cc setup time ? t vcs 50 ? ? s rise time to v id * 2 ?t vidr 500 ? ? ns rise time to v acc * 3 ?t vaccr 500 ? ? ns voltage transition time * 2 ?t vlht 4??s write pulse width* 2 ?t wpp 100 ? ? s oe setup time to we active* 2 ?t oesp 4??s ce setup time to we active* 2 ?t csp 4??s
96m page flash memory for mcp 16 (96m flash for mcp) smcp0.5e (continued) *1: this does not include the preprogramming time. *2: this timing is for se ctor protection operation. *3: this timing is for acce lerated program operation. parameter symbols value unit jedec standard min. typ. max. recover time from ry/by ?t rb 0??ns reset pulse width ? t rp 500 ? ? ns reset high level period before read ?t rh 200 ? ? ns program/erase valid to ry/by delay ?t busy ? ? 90 ns delay time from embedded output enable ? t eoe ? ? 65 ns erase time-out time ? t tow 50 ? ? s erase tisuspend transition time ? t spd ? ? 20 s
96m page flash memory for mcp (96m flash for mcp) 17 smcp0.5e erase and programm ing performance note: test conditions t a = 25c,typical erase conditions t a = 25c, v cc = 2.9 v typical program conditions t a = 25c, v cc = 2.9 v, data = checker parameter limits unit comments min. typ. max. sector erase time ? 0.5 2 s excludes programming time prior to erasure word programming time ? 6 100 s excludes system-level overhead chip programming time ? 37.7 150 s excludes system-level overhead erase/program cycle 100,000 ? ? cycles ?
96m page flash memory for mcp 18 (96m flash for mcp) smcp0.5e read operation timing diagram (flash) we oe ce0 f t df t ce t oe outputs addresses addresses stable high-z output valid high-z t oeh t acc t rc t oh (ce1 f) note : it is required to set ce1 f = "l" and a 21 = " l" for read operation in ce1 f region.
96m page flash memory for mcp (96m flash for mcp) 19 smcp0.5e page read operation timing diagram (flash) hardware reset/read operation timing diagram (flash) same page addresses we oe ce0 a 21 to a 3 a 2 to a 0 output t rc t ce t acc aa ab ac ad ae af ag ah t prc t prc t oe t oeh t pacc t pacc t pacc high-z t oh t oh t oh t oh t oh t oh t oh t oh da db dc dh t df t prc t prc t prc t prc t prc t pacc t pacc t pacc dd de df t pacc dg (ce1) note : it is required to set ce1 f = "l" and a 21 = " l" for page read operation in ce1 f region. address ce0 reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh (ce1) note : it is required to set ce1 f = "l" and a 21 = " l" for hardware reset/read operation in ce1 f region.
96m page flash memory for mcp 20 (96m flash for mcp) smcp0.5e alternate we controlled program operation timing diagram (flash) notes :1.pa is address of the me mory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the da ta written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.ce1 f and a 21 must be the same behavior for alternate we controlled program operation in ce1 f region. t ch t wp t whwh1 t wc t ah ce0 f oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df (ce1 f)
96m page flash memory for mcp (96m flash for mcp) 21 smcp0.5e alternate ce ( ce0 f or ce1 f)controlled program operat ion timing diagram (flash) notes :1.pa is address of the me mory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the da ta written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.ce 1f and a 21 must be the same behavior for alternate ce controlled program operation in ce 1f region. t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd ce0 f (ce1 f)
96m page flash memory for mcp 22 (96m flash for mcp) smcp0.5e chip/sector erase operat ion timing diagram (flash) * : sa is the sector add ress for sector erase. v cc ce0 f oe addresses data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h 30h for sector erase (ce1 f) note : it is required to set ce1 f = "l" and a 21 = " l" for sector erase operation in ce1 f region.
96m page flash memory for mcp (96m flash for mcp) 23 smcp0.5e data polling during embedded algorithm operation timing diagram (flash) t oeh t oe t whwh1 or 2 oe t eoe we data t df t ch t ce high-z high-z dq 7 = valid data dq 6 to dq 0 valid data dq 7 * dq 7 dq 6 to dq 0 data dq 6 to dq 0 = output flag ce0 (ce1) * : dq 7 = valid data (the device has completed the embedded operation).
96m page flash memory for mcp 24 (96m flash for mcp) smcp0.5e ac waveforms for toggle bit i during embedded algorithm operations (flash) t dh t oe t ce ce0 we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph (ce1) * : dq 6 stops toggling (the device has completed the embedded operation). note : when ce0 f ="h"and ce1 f =" l", dq 6 toggles by the change of a 21
96m page flash memory for mcp (96m flash for mcp) 25 smcp0.5e ce0 dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) (ce1) back-to-back read/write timing diagram (flash) notes : 1.it is required to set ce1 f = "l" and a 21 ="l"for read/write in the bank including ce1 f region. 2.this is example of read fo r bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2
96m page flash memory for mcp 26 (96m flash for mcp) smcp0.5e ry/by timing diagram during program/erase operation timing diagram (flash) reset , ry/by timing diagram (flash) note : it is required to set ce1 f = "l" and a 21 ="l"for being active ce1 f region ce0 ry/by we the rising edge of the last we signal t busy entire programming or erase operations (ce1) t rp t rb t ready ry/by we reset
96m page flash memory for mcp (96m flash for mcp) 27 smcp0.5e sector group protection timing diagram (flash) spax : sector group address to be protected spay : next sector group address to be protected : note : it is required to set ce1 f = "l" and a 21 ="l"for selecting the sector group in ce1 f region t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 21 , a 20, a 19, a 18 , a 17, a 16, a 15 , a 14, a 13, a 12, a 11 a 6 , a 2 , a 0 a 5 , a 4 , a 3 , a 1 a 9 v cc oe v id v ih v id v ih we ce0 data spax 01h spay (ce1)
96m page flash memory for mcp 28 (96m flash for mcp) smcp0.5e unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce0 reset (ce1) temporary sector group unprotection timing diagram (flash) note : it is required to set ce1 f = "l" and a 21 ="l"for selecting sector group in ce1 f region
96m page flash memory for mcp (96m flash for mcp) 29 smcp0.5e v cc we oe ce0 reset t wc t wc t vlht t vidr t vcs time-out sgax sgax sgay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 2 , a 0 a 5 , a 4 , a 3 , a 1 (ce1) extended sector group protec tion timing diagram (flash) sgax : sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = s (min.) note : it is required to set ce1 f = "l" and a 21 ="l"for selecting sector group in ce1 f region
96m page flash memory for mcp 30 (96m flash for mcp) smcp0.5e accelerated program timing diagram (flash) 3 v acc v cc ce0 we t vlht program or erase command sequence t vlht t vcs t vaccr v acc t vlht acceleration period (ce1) note : it is required to set ce1 f = "l" and a 21 ="l"for accelerated program in ce1 f region
64m flash for mcp (64m flash-70 for mcp) 1 smcp0.4e flexible sector-erase archi tecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32 k words. ? individual-sector, mu ltiple-sector, or bulk-erase capability. sector architecture sa31 : 64kb (32kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 8kb (4kw) sa6 : 8kb (4kw) sa5 : 8kb (4kw) sa4 : 8kb (4kw) sa3 : 8kb (4kw) sa2 : 8kb (4kw) sa70 : 64kb (32kw) sa69 : 64kb (32kw) sa68 : 64kb (32kw) sa67 : 64kb (32kw) sa66 : 64kb (32kw) sa65 : 64kb (32kw) sa64 : 64kb (32kw) sa63 : 64kb (32kw) sa62 : 64kb (32kw) sa61 : 64kb (32kw) sa60 : 64kb (32kw) sa59 : 64kb (32kw) sa58 : 64kb (32kw) sa57 : 64kb (32kw) sa56 : 64kb (32kw) sa55 : 64kb (32kw) sa54 : 64kb (32kw) sa53 : 64kb (32kw) sa52 : 64kb (32kw) sa51 : 64kb (32kw) sa50 : 64kb (32kw) sa49 : 64kb (32kw) sa48 : 64kb (32kw) sa47 : 64kb (32kw) sa46 : 64kb (32kw) sa45 : 64kb (32kw) sa44 : 64kb (32kw) sa43 : 64kb (32kw) sa42 : 64kb (32kw) sa41 : 64kb (32kw) sa40 : 64kb (32kw) sa39 : 64kb (32kw) sa38 : 64kb (32kw) sa37 : 64kb (32kw) sa36 : 64kb (32kw) sa35 : 64kb (32kw) sa34 : 64kb (32kw) sa33 : 64kb (32kw) sa32 : 64kb (32kw) sa1 : 8kb (4kw) sa0 : 8kb (4kw) bank a bank b 070000h 078000h 060000h 068000h 050000h 058000h 040000h 048000h 030000h 038000h 020000h 028000h 010000h 018000h 007000h 008000h 005000h 006000h 003000h 004000h 001000h 002000h 000000h sa102 : 64kb (32kw) sa101 : 64kb (32kw) sa100 : 64kb (32kw) sa99 : 64kb (32kw) sa98 : 64kb (32kw) sa97 : 64kb (32kw) sa96 : 64kb (32kw) sa95 : 64kb (32kw) sa94 : 64kb (32kw) sa93 : 64kb (32kw) sa92 : 64kb (32kw) sa91 : 64kb (32kw) sa90 : 64kb (32kw) sa89 : 64kb (32kw) sa88 : 64kb (32kw) sa87 : 64kb (32kw) sa86 : 64kb (32kw) sa85 : 64kb (32kw) sa84 : 64kb (32kw) sa83 : 64kb (32kw) sa82 : 64kb (32kw) sa81 : 64kb (32kw) sa80 : 64kb (32kw) sa79 : 64kb (32kw) sa78 : 64kb (32kw) sa77 : 64kb (32kw) sa76 : 64kb (32kw) sa75 : 64kb (32kw) sa74 : 64kb (32kw) sa73 : 64kb (32kw) 3fffffh sa141 : 8kb (4kw) sa140 : 8kb (4kw) sa139 : 8kb (4kw) sa138 : 8kb (4kw) sa137 : 8kb (4kw) sa136 : 8kb (4kw) sa135 : 8kb (4kw) sa134 : 8kb (4kw) sa133 : 64kb (32kw) sa132 : 64kb (32kw) sa131 : 64kb (32kw) sa130 : 64kb (32kw) sa129 : 64kb (32kw) sa128 : 64kb (32kw) sa127 : 64kb (32kw) sa126 : 64kb (32kw) sa125 : 64kb (32kw) sa124 : 64kb (32kw) sa123 : 64kb (32kw) sa122 : 64kb (32kw) sa121 : 64kb (32kw) sa120 : 64kb (32kw) sa119 : 64kb (32kw) sa118 : 64kb (32kw) sa117 : 64kb (32kw) sa116 : 64kb (32kw) sa115 : 64kb (32kw) sa114 : 64kb (32kw) sa113 : 64kb (32kw) sa112 : 64kb (32kw) sa111 : 64kb (32kw) sa110 : 64kb (32kw) sa109 : 64kb (32kw) sa108 : 64kb (32kw) sa107 : 64kb (32kw) sa106 : 64kb (32kw) sa105 : 64kb (32kw) sa104 : 64kb (32kw) sa103 : 64kb (32kw) sa72 : 64kb (32kw) sa71 : 64kb (32kw) bank c bank d 3ff000h 3fe000h 3fd000h 3fc000h 3fb000h 3fa000h 3f9000h 0f0000h 0f8000h 0e0000h 0e8000h 0d0000h 0d8000h 0c0000h 0c8000h 0b0000h 0b8000h 0a0000h 0a8000h 090000h 098000h 088000h 080000h 170000h 178000h 160000h 168000h 150000h 158000h 140000h 148000h 130000h 138000h 120000h 128000h 110000h 118000h 100000h 108000h 1f0000h 1f8000h 1e0000h 1e8000h 1d0000h 1d8000h 1c0000h 1c8000h 1b0000h 1b8000h 1a0000h 1a8000h 190000h 198000h 188000h 180000h 270000h 278000h 260000h 268000h 250000h 258000h 240000h 248000h 230000h 238000h 220000h 228000h 210000h 218000h 208000h 2f0000h 2f8000h 2e0000h 2e8000h 2d0000h 2d8000h 2c0000h 2c8000h 2b0000h 2b8000h 2a0000h 2a8000h 290000h 298000h 288000h 280000h 370000h 378000h 360000h 368000h 350000h 358000h 340000h 348000h 330000h 338000h 320000h 328000h 310000h 318000h 300000h 308000h 3f0000h 3f8000h 3e0000h 3e8000h 3d0000h 3d8000h 3c0000h 3c8000h 3b0000h 3b8000h 3a0000h 3a8000h 390000h 398000h 388000h 380000h 200000h 1fffffh word mode word mode
64m flash for mcp 2 (64m flash-70 for mcp) smcp0.4e table 1 flexbank tm architecture table 2 example of vi rtual banks combination note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for ex ample, suppose that erasi ng is taking place at bo th bank a and bank b, neither bank a nor bank b is read out (they would out put the sequence flag once they were selected.) meanwhile the system would get to read from either ba nk c or bank d. table 3 simultaneous operation * : by writing erase suspend command on the bank addr ess of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of conv enience at simultaneous oper ation. actually, the bank consists of 4 banks, bank a, bank b, bankc and ba nk d. bank address (ba) meant to specify each of the banks. bank splits bank 1 bank 2 volume combination volume combination 1 8 mbit bank a 56 mbit remainder (bank b, c, d) 2 24 mbit bank b 40 mbit remainder (bank a, c, d) 3 24 mbit bank c 40 mbit remainder (bank a, b, d) 4 8 mbit bank d 56 mbit remainder (bank a, b, c) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 18 mbit bank a 8 8 kbyte/4 kword + 15 64 kbyte/32 kword 56 mbit bank b + bank c + bank d 8 8 kbyte/4 kword + 111 64 kbyte/32 kword 216 mbit bank a + bank d 16 8 kbyte/4 kword + 30 64 kbyte/32 kword 48 mbit bank b + bank c 96 64 kbyte/32 kword 3 24 mbit bank b 48 64 kbyte/32 kword 40 mbit bank a + bank c + bank d 16 8 kbyte/4 kword + 78 64 kbyte/32 kword 432 mbit bank a + bank b 8 8 kbyte/4 kword + 63 64 kbyte/32 kword 32 mbit bank c + bank d 8 8 kbyte/4 kword + 63 64 kbyte/32 kword case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
64m flash for mcp (64m flash-70 for mcp) 3 smcp0.4e table 4 sector address tables (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0000000000 000000h to 000fffh sa1 0000000001 001000h to 001fffh sa2 0000000010 002000h to 002fffh sa3 0000000011 003000h to 003fffh sa4 0000000100 004000h to 004fffh sa5 0000000101 005000h to 005fffh sa6 0000000110 006000h to 006fffh sa7 0000000111 007000h to 007fffh sa8 0000001xxx 008000h to 00ffffh sa9 0000010xxx 010000h to 017fffh sa10 0000011xxx 018000h to 01ffffh sa11 0000100xxx 020000h to 027fffh sa12 0000101xxx 028000h to 02ffffh sa13 0000110xxx 030000h to 037fffh sa14 0000111xxx 038000h to 03ffffh sa15 0001000xxx 040000h to 047fffh sa16 0001001xxx 048000h to 04ffffh sa17 0001010xxx 050000h to 057fffh sa18 0001011xxx 058000h to 05ffffh sa19 0001100xxx 060000h to 067fffh sa20 0001101xxx 068000h to 06ffffh sa21 0001110xxx 070000h to 077fffh sa22 0001111xxx 078000h to 07ffffh
64m flash for mcp 4 (64m flash-70 for mcp) smcp0.4e (continued) (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa23 0010000xxx 080000h to 087fffh sa24 0010001xxx 088000h to 08ffffh sa25 0010010xxx 090000h to 097fffh sa26 0010011xxx 098000h to 09ffffh sa27 0010100xxx 0a 0000h to 0a7fffh sa28 0010101xxx 0a 8000h to 0affffh sa29 0010110xxx 0b 0000h to 0b7fffh sa30 0010111xxx 0b 8000h to 0bffffh sa31 0011000xxx 0c 0000h to 0c7fffh sa32 0011001xxx 0c 8000h to 0cffffh sa33 0011010xxx 0d 0000h to 0d7fffh sa34 0011011xxx 0d 8000h to 0dffffh sa35 0011100xxx 0e 0000h to 0e7fffh sa36 0011101xxx 0e 8000h to 0effffh sa37 0011110xxx 0f 0000h to 0f7fffh sa38 0011111xxx 0f 8000h to 0fffffh sa39 0100000xxx 100000h to 107fffh sa40 0100001xxx 108000h to 10ffffh sa41 0100010xxx 110000h to 117fffh sa42 0100011xxx 118000h to 11ffffh sa43 0100100xxx 120000h to 127fffh sa44 0100101xxx 128000h to 12ffffh sa45 0100110xxx 130000h to 137fffh sa46 0100111xxx 138000h to 13ffffh sa47 0101000xxx 140000h to 147fffh sa48 0101001xxx 148000h to 14ffffh sa49 0101010xxx 150000h to 157fffh sa50 0101011xxx 158000h to 15ffffh sa51 0101100xxx 160000h to 167fffh sa52 0101101xxx 168000h to 16ffffh sa53 0101110xxx 170000h to 177fffh sa54 0101111xxx 178000h to 17ffffh sa55 0110000xxx 180000h to 187fffh sa56 0110001xxx 188000h to 18ffffh sa57 0110010xxx 190000h to 197fffh sa58 0110011xxx 198000h to 19ffffh sa59 0110100xxx 1a 0000h to 1a7fffh sa60 0110101xxx 1a 8000h to 1affffh sa61 0110110xxx 1b 0000h to 1b7fffh sa62 0110111xxx 1b 8000h to 1bffffh sa63 0111000xxx 1c 0000h to 1c7fffh sa64 0111001xxx 1c 8000h to 1cffffh sa65 0111010xxx 1d 0000h to 1d7fffh sa66 0111011xxx 1d 8000h to 1dffffh sa67 0111100xxx 1e 0000h to 1e7fffh sa68 0111101xxx 1e 8000h to 1effffh sa69 0111110xxx 1f 0000h to 1f7fffh sa70 0111111xxx 1f 8000h to 1fffffh
64m flash for mcp (64m flash-70 for mcp) 5 smcp0.4e (continued) (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa71 1000000xxx 200000h to 207fffh sa72 1000001xxx 208000h to 20ffffh sa73 1000010xxx 210000h to 217fffh sa74 1000011xxx 218000h to 21ffffh sa75 1000100xxx 220000h to 227fffh sa76 1000101xxx 228000h to 22ffffh sa77 1000110xxx 230000h to 237fffh sa78 1000111xxx 238000h to 23ffffh sa79 1001000xxx 240000h to 247fffh sa80 1001001xxx 248000h to 24ffffh sa81 1001010xxx 250000h to 257fffh sa82 1001011xxx 258000h to 25ffffh sa83 1001100xxx 260000h to 267fffh sa84 1001101xxx 268000h to 26ffffh sa85 1001110xxx 270000h to 277fffh sa86 1001111xxx 278000h to 27ffffh sa87 1010000xxx 280000h to 287fffh sa88 1010001xxx 288000h to 28ffffh sa89 1010010xxx 290000h to 297fffh sa90 1010011xxx 298000h to 29ffffh sa91 1010100xxx 2a 0000h to 2a7fffh sa92 1010101xxx 2a 8000h to 2affffh sa93 1010110xxx 2b 0000h to 2b7fffh sa94 1010111xxx 2b 8000h to 2bffffh sa95 1011000xxx 2c 0000h to 2c7fffh sa96 1011001xxx 2c 8000h to 2cffffh sa97 1011010xxx 2d 0000h to 2d7fffh sa98 1011011xxx 2d 8000h to 2dffffh sa99 1011100xxx 2e 0000h to 2e7fffh sa1001011101xxx 2e 8000h to 2effffh sa1011011110xxx 2f 0000h to 2f7fffh sa1021011111xxx 2f 8000h to 2fffffh sa1031100000xxx 300000h to 307fffh sa1041100001xxx 308000h to 30ffffh sa1051100010xxx 310000h to 317fffh sa1061100011xxx 318000h to 31ffffh sa1071100100xxx 320000h to 327fffh sa1081100101xxx 328000h to 32ffffh sa1091100110xxx 330000h to 337fffh sa1101100111xxx 338000h to 33ffffh sa1111101000xxx 340000h to 347fffh sa1121101001xxx 348000h to 34ffffh sa1131101010xxx 350000h to 357fffh sa1141101011xxx 358000h to 35ffffh sa1151101100xxx 360000h to 367fffh sa1161101101xxx 368000h to 36ffffh sa1171101110xxx 370000h to 377fffh sa1181101111xxx 378000h to 37ffffh
64m flash for mcp 6 (64m flash-70 for mcp) smcp0.4e (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1191110000xxx 380000h to 387fffh sa1201110001xxx 388000h to 38ffffh sa1211110010xxx 390000h to 397fffh sa1221110011xxx 398000h to 39ffffh sa1231110100xxx 3a 0000h to 3a7fffh sa1241110101xxx 3a 8000h to 3affffh sa1251110110xxx 3b 0000h to 3b7fffh sa1261110111xxx 3b 8000h to 3bffffh sa1271111000xxx 3c 0000h to 3c7fffh sa1281111001xxx 3c 8000h to 3cffffh sa1291111010xxx 3d 0000h to 3d7fffh sa1301111011xxx 3d 8000h to 3dffffh sa1311111100xxx 3e 0000h to 3e7fffh sa1321111101xxx 3e 8000h to 3effffh sa1331111110xxx 3f 0000h to 3f7fffh sa1341111111000 3f 8000h to 3f8fffh sa1351111111001 3f 9000h to 3f9fffh sa1361111111010 3fa 000h to 3fafffh sa1371111111011 3fb 000h to 3fbfffh sa1381111111100 3fc 000h to 3fcfffh sa1391111111101 3fd 000h to 3fdfffh sa1401111111110 3fe 000h to 3fefffh sa1411111111111 3ff 000h to 3fffffh
64m flash for mcp (64m flash-70 for mcp) 7 smcp0.4e table 5 sector group addresses sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 01 xxx sa8 to sa10 10 11 sga9 00001 xxxxx sa11 to sa14 sga10 00010 xxxxx sa15 to sa18 sga11 00011 xxxxx sa19 to sa22 sga12 00100 xxxxx sa23 to sa26 sga13 00101 xxxxx sa27 to sa30 sga14 00110 xxxxx sa31 to sa34 sga15 00111 xxxxx sa35 to sa38 sga16 01000 xxxxx sa39 to sa42 sga17 01001 xxxxx sa43 to sa46 sga18 01010 xxxxx sa47 to sa50 sga19 01011 xxxxx sa51 to sa54 sga20 01100 xxxxx sa55 to sa58 sga21 01101 xxxxx sa59 to sa62 sga22 01110 xxxxx sa63 to sa66 sga23 01111 xxxxx sa67 to sa70 sga24 10000 xxxxx sa71 to sa74 sga25 10001 xxxxx sa75 to sa78 sga26 10010 xxxxx sa79 to sa82 sga27 10011 xxxxx sa83 to sa86 sga28 10100 xxxxx sa87 to sa90 sga29 10101 xxxxx sa91 to sa94 sga30 10110 xxxxx sa95 to sa98 sga31 10111 xxxxx sa99 to sa102 sga32 11000 xxxxx sa103 to sa106 sga33 11001 xxxxx sa107 to sa110 sga34 11010 xxxxx sa111 to sa114 sga35 11011 xxxxx sa115 to sa118 sga36 11100 xxxxx sa119 to sa122 sga37 11101 xxxxx sa123 to sa126 sga38 11110 xxxxx sa127 to sa130 sga39 11111 00 xxx sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
64m flash for mcp 8 (64m flash-70 for mcp) smcp0.4e table 6 flash memo ry autoselect codes legend: l = v il , h = v ih . see dc characteristics for voltage levels. *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : a read cycle at address (ba) 01h outputs device code. when 227eh was ou tput, this indicate s that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the addres s of (ba) 0eh, as well as at (ba) 0fh. type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufacture?s codeba lllll 04h device code ba llllh227eh extended device code * 2 ba lhhhl 2202h ba lhhhh 2201h sector group protection sector group addresses lllhl 01h* 1
64m flash for mcp (64m flash-70 for mcp) 9 smcp0.4e table 7 flash memory command definitions (continued) command sequence bus write cycles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1xxxhf0h?????????? read/reset 3 555h aah 2aah 55h 555h f0h ra rd ? ? ? ? autoselect 3 555h aah 2aah 55h (ba) 555h 90h?????? program 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? program suspend 1 bab0h?????????? program resume 1 ba30h?????????? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 bab0h?????????? erase resume 1 ba30h?????????? extended sector group protection * 2 4 xxxh 60h spa 60h spa 40h spa sd ? ? ? ? set to fast mode 3 555h aah 2aah 55h 555h 20h ? ? ? ? ? ? fast program * 1 2xxxha0hpapd???????? reset from fast mode * 1 2 ba 90h xxxh * 4 f0h ???????? query 1 (ba) 55h 98h?????????? hi-rom entry 3 555h aah 2aah 55h 555h 88h ? ? ? ? ? ? hi-rom program * 3 4 555h aah 2aah 55h 555h a0h (hra ) pa pd???? hi-rom exit * 3 4 555h aah 2aah 55h (hrba ) 5 55h 90h xxxh 00h ? ? ? ?
64m flash for mcp 10 (64m flash-70 for mcp) smcp0.4e (continued) *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: this command is valid during hi-rom mode. *4: the data ?00h? is also acceptable. notes: 1. address bits a 21 to a 11 = x = ?h? or ?l? for all address comm ands except or program address (pa), sector address (sa), and bank addre ss (ba), and sector group address (spa). 2. bus operations are defined in device bus operation. 3. ra =address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 21 , a 20 , a 19 ) 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. 5. spa =sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0). sd = sector group protection ve rify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. hra = address of the hi-rom area: 000000h to 00007fh 7. hrba = bank address of the hi-rom area (a 21 = a 20 = a 19 = v il ) 8. the system should generate the following address patterns: 555h or 2aah to addresses a 10 to a 0 9. both read/reset commands are functionally eq uivalent, resetting the device to the read mode. 10. the command combinations not de scribed in this table are illegal.
64m flash for mcp (64m flash-70 for mcp) 11 smcp0.4e electrical characteristics ( ac characteristics) read only operations characteristics (flash) note: test conditions? output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc f timing measurement reference level input: 0.5v cc f output: 0.5v cc f parameter symbol condition value (note) unit jedec standard min. max. read cycle time t avav t rc ?70?ns address to output delay t avqv t acc ce f = v il oe = v il ?70ns chip enable to output delay t elqv t ce foe = v il ?70ns output enable to output delay t glqv t oe ??30ns chip enable to output high-z t ehqz t df ??25ns output enable to output high-z t ghqz t df ??25ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh ?0?ns reset pin low to read mode ? t ready ??20s
64m flash for mcp 12 (64m flash-70 for mcp) smcp0.4e read operation timing diagram (flash) hardware reset/read operation timing diagram (flash) address address stable high-z high-z cef oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh address cef reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh
64m flash for mcp (64m flash-70 for mcp) 13 smcp0.4e write / erase / program operations (flash) (continued) parameter symbol value unit jedec standard min. typ. max. write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 12 ?? ns address hold time t wlax t ah 30 ?? ns address hold time from cef or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 25 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns cef high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns cef setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns cef hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 35 ?? ns cef pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 20 ?? ns cef pulse width high t ehel t cph 20 ?? ns programming operation t whwh1 t whwh1 ? 6 ? s sector erase operation * 1 t whwh2 t whwh2 ? 0.5 ? s v cc f setup time ? t vcs 50 ?? s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? ns voltage transition time * 2 ? t vlht 4 ?? s write pulse width * 2 ? t wpp 100 ?? s
64m flash for mcp 14 (64m flash-70 for mcp) smcp0.4e (continued) *1: this does not include preprogramming time. *2: this timing is for sector group protection operation. *3: this timing is for acce lerated program operation. parameter symbol value unit jedec standard min. typ. max. oe setup time to we active * 2 ? t oesp 4 ?? s cef setup time to we active * 2 ? t csp 4 ?? s recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns reset high level period before read ? t rh 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 70 ns erase time-out time ? t tow 50 ? s erase suspend transition time ? t spd ?? 20 s
64m flash for mcp (64m flash-70 for mcp) 15 smcp0.4e write cycle (we control) (flash) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the dat a written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. address data cef oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch
64m flash for mcp 16 (64m flash-70 for mcp) smcp0.4e write cycle (ce f control) (flash) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycl es out of four bus cycle sequence. address data we oe cef 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh
64m flash for mcp (64m flash-70 for mcp) 17 smcp0.4e ac waveforms chip/sector erase operations (flash) address data v cc f cef oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h 30h for sector erase * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase.
64m flash for mcp 18 (64m flash-70 for mcp) smcp0.4e ac waveforms for data polling during embedded algor ithm operations (flash) * : dq 7 = valid data (the device has completed the embedded operation) . t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 cef dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data *
64m flash for mcp (64m flash-70 for mcp) 19 smcp0.4e ac waveforms for toggle bit during embe dded algorithm operations (flash) t dh t oe t ce cef we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph * : dq 6 stops toggling (the device has co mpleted the embedded operation).
64m flash for mcp 20 (64m flash-70 for mcp) smcp0.4e back-to-back read/write timing diagram (flash) cef dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2
64m flash for mcp (64m flash-70 for mcp) 21 smcp0.4e ry/by timing diagram during write/erase operations (flash) reset , ry/by timing diagram (flash) cef ry/by we the rising edge of the last we signal t busy entire programming or erase operations t rp t rb t ready ry/by we reset
64m flash for mcp 22 (64m flash-70 for mcp) smcp0.4e temporary sector unprotection (flash) acceleration mode timing diagram (flash) unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc f v id v ih we ry/by cef reset v ih wp/acc v cc f cef we ry/by t vlht program or erase command sequence t vlht t vcs t vaccr vacc t vlht acceleration period
64m flash for mcp (64m flash-70 for mcp) 23 smcp0.4e extended sector grou p protection (flash) spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 s (min.) v cc f we oe cef reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1
64m flash for mcp 24 (64m flash-70 for mcp) smcp0.4e erase and pro gramming performance (flash) typical erase conditions t a = 25c, vccf_1 & vccf_2 = 2.9v typical program conditions t a = 25c, vccf_1 & vccf_2 = 2.9v data= checker parameter value unit remarks min. typ. max. sector erase time ? 0.5 2.0 s excludes programming time prior to erasure word programming time ? 6 100 s excludes system-level overhead chip programming time ? ? 200 s excludes system-level overhead erase/program cycle 100,000 ? ? cycle
64m fcram for mcp (64m fcram-65 for mcp) 1 smcp0.1e fcram power down program key table basic key table available key table definition a16 a17 a19 a20 a21 key mode select area select a19 a20 a21 area lll bottom *2 l h x reserved h l x reserved hhh top *3 a16 a17 mode ll nap *4 l h reserved hl16m partial hh sleep *4, *5 mode a16 a17 a19 a20 a21 data retention area mode select area select nap l l x x x none 16m partial h l l l l bottom 16m only h l h h h top 16m only sleep h h x x x none notes *1: the power down program can be performed one time after compliance of power-up timings and it should not be re-programmed after regular read or write. unspecified addresses, a0 to a15, can be either high or low during the programming. the reserved key should not be used. *2: bottom area is from the lo west address location. (i.e., a ( 20:0 ) = l) *3: top area is from the highest address location. (i.e., a ( 20:0 ) = h) *4: nap and sleep do not retain the data and area select is ignored. *5: default state. power down program to this sleep mode can be omitted.
64m fcram for mcp 2 (64m fcram-65 for mcp) smcp0.1e electrical characteristics ( ac characteristics) ? read operation (fcram) notes *1: the output load is 30pf. *2: the output load is 5pf. *3: the t ce is applicable if oe is brought to low before ce 1r goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. *4: applicable only to a0 and a1 when both ce 1r and oe are kept at low for the address access. *5: applicable if oe is brought to low before ce 1r goes low. *6: the t aso , t clol (min) and t op (min) are reference values when the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe become longer by the amount of subtracting actual valu e from specified minimum value. for example, if actual t aso , t aso (actual), is shorter than sp ecified minimum value, t aso (min), during oe control access (ie., ce 1r stays low), the t oe become t oe (max) + t aso (min) ? t aso (actual). *7: the t aso ( abs ) and t op ( abs) is the absolute minimum value during oe control access. *8: the t ax is applicable when both a0 and a1 are switched from previous state. *9: if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) ? t clol (actual) or t rc (min) ? t op (actual). *10: maximum value is applicable if ce 1r is kept at low. parameter symbol value unit notes min. max. read cycle time t rc 70 ? ns chip enable access time t ce ?65ns*1,*3 output enable access time t oe ?40ns*1 address access time t aa ?65ns*1,*4 output data hold time t oh 5?ns*1 ce 1r low to output low-z t clz 5?ns*2 oe low to output low-z t olz 0?ns*2 ce 1r high to output high-z t chz ?20ns*2 oe high to output high-z t ohz ?20ns*2 address setup time to ce 1r low t asc ?5 ? ns *5 address setup time to oe t aso 25 ? ns *3,*6 t aso(abs) 10 ? ns *7 lb / ub setup time to ce1 r low t bsc ?5 ? *5 lb / ub setup time to oe low t bso 10 ? address invalid time t ax ?5ns*4,*8 address hold time from ce1 r low t clah 70 ? ns *4 address hold time from oe low t olah 45 ? ns *4,*9 address hold time from ce1 r high t chah ?5 ? ns address hold time from oe high t ohah ?5 ? ns lb / ub hold time from ce1 r high t chbh ?5 ? lb / ub hold time from oe high t ohbh ?5 ? ce 1r low to oe low delay time t clol 25 1000 ns *3,*6,*9,*10 oe low to ce 1r high delay time t olch 45 ? ns *9 ce 1r high pulse width t cp 12 ? ns oe high pulse width t op 25 1000 ns *6,*9,*10 t op(abs) 12 ? ns *7
64m fcram for mcp (64m fcram-65 for mcp) 3 smcp0.1e ? write operation (fcram) notes: *1: minimum value must be equal or greater then the sum of actual t cw (or t wp ) and t wrc (or t wr ). *2: new write address is valid from either ce 1r or we is bought to high. *3: the t oeh is specified from end of t wc( min). the t oeh (min) is a reference value when the access time is determined by t oe . if actual value, t oeh (actual) is shorter than specified minimum value, t oe become longer by the amount of subtracting actual value from specified minimum value. *4: the t oeh (max) is applicable if ce1 r is kept at low and both we and oe are kept at high. *5: the t oeh ( abs ) is the absolute minimum value if write cycle is termnated by we and ce1 r stays low. *6: t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min), we low must be asserted after t rc (min) from ce 1r low. in other words, read oper ation is initiated if t ohcl (min) is not satisfied. *7: applicable if ce 1r stays low after read operation. *8: t cw and t wp is applicable if write ope ration is in itiated by ce 1r and we , respectively. *9: t wrc and t wr is applicable if write oper ation is terminated by ce 1r and we , respectively. the t wr (min) can be ignored if ce 1r is brought to high together or after we is brought to high. in such case, the t cp (min) must be satisfied. parameter symbol value unit notes min. max. write cycle time t wc 70 ? ns *1 address setup time t as 0?ns*2 address hold time t ah 35 ? ns *2 ce 1r write setup time t cs 0 1000 ns ce 1r write hold time t ch 0 1000 ns we setup time t ws 0?ns we hold time t wh 0?ns lb and ub setup time t bs ?5 ? ns lb and ub hold time t bh ?5 ? ns oe setup time t oes 0 1000 ns *3 oe hold time t oeh 25 1000 ns *3, *4 t oeh(abs ) 12 ? ns *5 oe high to ce 1r low setup time t ohcl ?5 ? ns *6 oe high to address hold time t ohah ?5 ? ns *7 ce 1r write pulse width t cw 45 ? ns *1, *8 we write pulse width t wp 45 ? ns *1, *8 ce 1r write recovery time t wrc 10 ? ns *1, *9 we write recovery time t wr 10 1000 ns *1, *3, *9 data setup time t ds 15 ? ns data hold time t dh 0?ns ce 1r high pulse width t cp 12 ? ns *9
64m fcram for mcp 4 (64m fcram-65 for mcp) smcp0.1e power down and power down program param eters (fcram) notes: *1: applicable to down program. other timing parameters (fcram) notes: *1: it may write some data into any address location if t chwx is not satisfied. *2: must satisfy t chh (min) after t c2lh (min). *3: requires powe r down mode entry and exit after t c2hl . *4: the input trasition time(t t ) at ac testing is 5ns as shown in below. if actual t t is longer than 5ns, it may violate ac specification of some timing parameters. ac test conditions (fcram) parameter symbol value unit note min. max. ce2r low setup time for power down entry t csp 10 ? ns ce2r low hold time a fter power down entry t c2lp 70 ? ns ce 1r high hold time follo wing ce2r high after power down exit(sleep mode only) t chh 350 ? s ce 1r high setup time following ce2r high after power down exit(except for sleep mode) t chhn 1? s ce1 r high setup time following ce2r high after power down exit t chs 10 ? ns ce1 r high to pe low setup time t eps 70 ? ns *1 pe power down program pulse width t ep 70 ? ns *1 pe high to ce1 r low hold time t eph 70 ? ns *1 address setup time to pe high t eas 15 ? ns *1 address setup time from pe high t eah 0?ns*1 parameter symbol value unit note min. max. ce 1r high to oe invalid time for standby entry t chox 10 ? ns ce 1r high to we invalid time for standby entry t chwx 10 ? ns *1 ce2r low hold time after power-up t c2lh 50 ? s*2 ce2r high hold time after power-up t c2hl 50 ? s*3 ce 1r high hold time follo wing ce2r high after power-up t chh 350 ? s*2 input transition time t t 125ns*4 symbol description test setup value unit note v ih input high level v cc r = 2.7v to 3.1v 2.3 v v il input low level v cc r = 2.7v to 3.1v 0.4 v v ref input timing measurement level v cc r = 2.7v to 3.1v 1.3 v t t input transition time between v il and v ih 5ns
64m fcram for mcp (64m fcram-65 for mcp) 5 smcp0.1e read timing #1 (oe control access) (fcram) note: ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1r and oe are low. t ce valid data output address ce 1r dq (output) lb / ub t ohz t ohz t oe t rc t olz t olz t ohah t op address valid t aso t oe valid data output address valid t clol t rc t oh t oh t ohah t aso t olch oe t bso t bso t ohbh t ohbh
64m fcram for mcp 6 (64m fcram-65 for mcp) smcp0.1e read timing #2 (ce 1r control access) (fcram) note: ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1r and oe are low. t ce t ce valid data output address ce 1r dq (output) oe t chz t chz t rc t clz t chah t cp address valid t asc valid data output address valid t asc t chah t clz t oh t oh t rc lb / ub t bsc t bsc t chbh t chbh
64m fcram for mcp (64m fcram-65 for mcp) 7 smcp0.1e read timing #3 (address access after oe control access) (fcram) note: ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1r and oe are low. valid data output address (a2-a0) ce 1r dq (output) oe t ohz t oe t rc t olz t olah address valid t ax valid data output address valid t rc t oh t oh t ohah t aso t aa address (a21-a3) address valid address valid (no change) lb / ub t bso t ohbh
64m fcram for mcp 8 (64m fcram-65 for mcp) smcp0.1e read timing #4 (address access after ce 1r control access) (fcram) note: ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1r and oe are low. t aa t ce valid data output address (a2-a0) ce 1r dq (output) oe t chz t rc t clz t ax address valid valid data output address valid t asc t chah t oh t oh t rc t clah address (a21-a3) address valid address valid (no change) lb / ub t bsc t chbh
64m fcram for mcp (64m fcram-65 for mcp) 9 smcp0.1e write timing #1 (ce 1r control) (fcram) note: ce2r and pe must be high for write cycle. t as valid data input address ce 1r dq (input) we t dh t ds t wc t wrc t ws t cw t wh ub , lb t bh t bs address valid t as t ah t ws t bs oe t ohcl
64m fcram for mcp 10 (64m fcram-65 for mcp) smcp0.1e write timing #2-1 (we control,single write operetion) (fcram) note: ce2r and pe must be high for write cycle. t as address we ce 1r t wc t cs t wp ub , lb t bs address valid t as t ah t wr t bh t cp valid data input dq (input) t dh t ds oe t oes t ohcl t ohah t ohz t ch t ohbh
64m fcram for mcp (64m fcram-65 for mcp) 11 smcp0.1e write timing #2-2 (we control,continuous write operetion) (fcram) note: ce2r and pe must be high for write cycle. t as address we ce 1r t wc t cs t wp ub , lb address valid t as t ah t wr t bh t bs valid data input dq (input) t dh t ds oe t oes t ohcl t ohah t ohz t bs t bh
64m fcram for mcp 12 (64m fcram-65 for mcp) smcp0.1e read / write timing #1-1 (ce 1r control) (fcram) note: write address is valid from either ce 1r or we of last falling edge. read data output address ce 1r dq we t wc t cw oe t ohcl ub , lb t bs t chah t cp write address t as t ah write data input t ds t chz t oh t wrc t clol t bh t asc read address t ws t wh t ws t wh t dh t olz t chbh t bso
64m fcram for mcp (64m fcram-65 for mcp) 13 smcp0.1e read / write timing #1-2 (ce 1r control) (fcram) note: the t oeh is specified from the time satisfied both t wrc and t wr (min). read data output address ce 1r dq we t rc t cp t ws oe t wh t ohcl t oeh ub , lb t bh t bs write address t chah t wrc (min) write data input t dh t oh t as t ws read address t chz t clz t ce t asc t wh t wrc t bsc t chbh
64m fcram for mcp 14 (64m fcram-65 for mcp) smcp0.1e read(oe control) / write(we control) timing #2-1 (fcram) note: ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled by oe . t wr read data output address ce 1r dq we t wc t wp oe t oes ub , lb t bs write address t as t ah write data input t dh t ds t ohz t oh low t oeh t bh t aso t ohah read address t olz t ohbh t bso
64m fcram for mcp (64m fcram-65 for mcp) 15 smcp0.1e read(oe control) / write(we control) timing #2-2 note: ce 1 r can be tied to low for we and oe controlled operation. when ce 1 r is tied to low, output is exclusively controlled by oe . power down program timing (fcram) note: ce2r must be high for power down programming. any other inputs not specified ab ove can be either high or low. read data output address ce 1r dq we low oe t oes t oeh ub , lb t bh write address write data input t dh t oh t as read address valid t ohz t olz t oe t ohah t aso t rc t wr t ohbh t bs t bso t eps ce 1r pe t ep t eph t eas address (a21-a16) key t eah
64m fcram for mcp 16 (64m fcram-65 for mcp) smcp0.1e power down entry and exit timing (fcram) note: this power down mode can be also used for power-up #2 below except that t chhn can not be used at power- up timing. power-up timing #1 (fcram) note: the t c2lh specifies after v cc r reaches specified minimum level. power-up timing #2 (fcram) note: the t c2hl specifies from ce2r low to high transition after v cc r reaches specified minimum level. ce 1r must be brought to high prior to or together with ce2r low to high transition. t csp ce 1r power down entry ce2r t c2lp t chh (t chhn ) power down mode power down exit t chs dq high-z t c2lh ce 1r v cc r v cc r min 0v ce2r t chh t chs t c2hl ce 1r v cc r v cc r min 0v ce2r t chh t chs t csp t c2lp t c2hl
64m fcram for mcp (64m fcram-65 for mcp) 17 smcp0.1e standby entry timing after read or write (fcram) note: both t chox and t chwx define the earliest entry timing for standby mode . if either of timing is not satisfied, it takes t rc (min) period from either last address transition of a0 and a1, or ce 1r low to high transition. t chox ce 1r oe we active (read) standby active (write) standby t chwx
64m fcram for mcp 18 (64m fcram-65 for mcp) smcp0.1e data retention low v cc r characteristics (fcram) notes: *1: 2.0 v ih v cc r+0.3v data retention timing parameter symbol t est conditions value unit min. max. v cc r data retention supply voltage v dr ce 1r = ce2r v cc r ? 0.2v or, ce 1r = ce2r = v ih, 2.3 3.1 v v cc r data retention supply current i dr 2.3v v cc r 2.7v, v in = v ih (*1) or v il ce 1r = ce2r = v ih (*1) , i out =0ma ?1.5ma i dr1 2.3v v cc r 2.7v, v in 0.2v or v in v cc r ? 0.2v, ce 1r = ce2r v cc r ? 0.2v, i out =0ma ?150 a data retention setup time t drs 2.7v v cc r 3.1v at data retention entry 0?ns data retention recovery time t drr 2.7v v cc r 3.1v after data retention 200 ? ns v cc r voltage transition time ? v/ ? t0.2?v/ s ? v/ ? t ce 1r t drr data retention mode t drs > v cc r- 0.2v or v ih( *1 ) min v cc r 2.7v 3.1v 0.4v 2.3v v ss ? v/ ? t ce2r data bus must be in high-z at data retention entry.
mb84vfaf5f5j1-70 14 (mb84vfaf5f5j1 smcp0.2e) pin capacitance note: test conditions ta = 25c, f = 1.0 mhz handling of package please handle this package carefully since the sides of package create acute angles. caution ? the high voltage (v id ) cannot apply to address pins and control pins except reset _1 or reset _2. exception is when autoselect and sector group protec t function are used, then the high voltage (v id ) can be applied to reset _1 or reset _2. ? without the high voltage (v id ) , sector group protection can be achi eved by using ?extended sector group protection? command. parameter symbol condition value unit min. typ. max. input capacitance c in v in = 0 ?? t.b.d. pf output capacitance c out v out = 0 ?? t.b.d. pf control pin capacitance c in2 v in = 0 ?? t.b.d. pf
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 15 ordering information mb84vfaf5f5j1 -70 pbs device number/descripton 96mega-bit (4m x 16bit + 2m x 16bit ) page mode dual operation flash memory 3.0v-only read, program, and erase 64mega-bit (4m x 16bit) dual operation flash memory 3.0v-only read, program, and erase 64mega-bit (2m x 16bit) fcram package type pbs = 115-ball bga speed option
mb84vfaf5f5j1-70 16 (mb84vfaf5f5j1 smcp0.2e) package dimension 115-pin plastic fbga (bga-115p-mxx) dimensions in mm (inches). now printing
mb84vfaf5f5j1-70 (mb84vfaf5f5j1 smcp0.2e) 17 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0211 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to c onsult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semic onductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility fo r infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices ar e intended for use in standard applications (computers, offi ce automation and other office equipments, industrial, comm unications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating c ontrols, medical devices for life support, etc.) are requested to consul t with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a cert ain rate of failure. you must protect against injury, da mage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and othe r abnormal operating conditions. if any products described in th is document repr esent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign tr ade control law of japan, the prior authorization by japanese government s hould be required for export of those products from japan.

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